Subject: Digital System Design

Topic: Introduction to VHDL

Difficulty: High

VHDL Code for Half Subtractor:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hs1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

diff : out STD_LOGIC;

borrow : out STD_LOGIC);

end hs1;

architecture Behavioral of hs1 is

begin

diff<=a xor b;

borrow<=(not a) and b;

end Behavioral;