Subject: Digital System Design

Topic: Design of Sequential circuits using VHDL

Difficulty: High

VHDL Code for 4 bit Ring Counter:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Ring_counter is

Port ( CLOCK : in  STD_LOGIC;

       RESET : in  STD_LOGIC;

       Q : out  STD_LOGIC_VECTOR (3 downto 0));

end Ring_counter;

architecture Behavioral of Ring_counter is

signal q_tmp: std_logic_vector(3 downto 0):= "0000";

begin

process(CLOCK,RESET)

begin

if RESET = …