Subject: Digital System Design

Topic: Design of Sequential circuits using VHDL

Difficulty: High

VHDL code for Sequence detector (101) using mealy state machine:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mealy is

Port ( clk : in STD_LOGIC;

din : in STD_LOGIC;

rst : in STD_LOGIC;

dout : out STD_LOGIC);

end mealy;

architecture Behavioral of mealy is

type state is (st0, st1, st2, st3);

signal …