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Describe the basic block diagram of the phase locked loop (PLL).

Subject: Liner Integrated Circuits

Topic: Special Purpose Integrated Circuits

Difficulty: Low

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Phased Locked Loop (PLL)


A phase locked loop is basically a closed loop system designed to lock the output frequency and phase to the frequency and phase of an input signal.

They are used in applications such as frequency synthesis, frequency modulation/demodulation, AM detection, tracking filters, FSK demodulator, tone detector etc.

Following figure shows the block diagram of PLL. PLL

It consists of

  • Phase detector
  • Low pass filter
  • Voltage Controlled Oscillator (VCO)

The phase detector compares the input frequency fi with the feedback frequency fo and generates an output signal which is a function of the difference between the phases of the two input signals. The output signal of the phase detector is a dc voltage. The output of phase detector is applied to low-pass filter to remove high frequency noise from the dc voltage. The output of low pass filter without high frequency noise is often referred to as error voltage or control voltage for VCO.

When control voltage is zero, VCO is in free running mode and its output frequency is called as centre frequency fo. The non-zero control voltage results in a shift in the VCO frequency from its free-running frequency, fo to a frequency f, given by

f = fo + Kv Vc where Kv is the voltage to frequency transfer coefficient of the VCO. The error or control voltage applied as an – input to the VCO, forces the VCO to change its output frequency in the direction that reduces the difference between the input frequency and the output frequency of VCO.

This action, commonly known as capturing, continues till the output frequency of VCO is same as the input signal frequency. Once the two frequencies are same, the circuit is said to be locked. In locked condition, phase detector generates a constant dc level which is required to shift the output frequency of VCO from centre frequency to the input frequency. Once locked, PLL tracks the frequency changes of the input signal. Thus, a PLL goes through three states. : free running, capture and phase lock.

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