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Question: Digital Logic Design & Analysis : Question Paper May 2017 - Computer Engineering (Semester 3) | Mumbai University (MU)
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Digital Logic Design & Analysis - May 2017

Computer Engineering (Semester 3)


TOTAL MARKS: 80

TOTAL TIME: 3 HOURS


(1) Question 1 is compulsory.

(2) Attempt any three from the remaining five questions.

(3) Each question carries 20 marks

(4) Within a question, each sub-question carries equal marks.


1 a) Convert $(-124)_{10}$ to its equivalent sign magnitude form ( 2 marks)

b) Convert decimal 214.32 into base 7. -----( 2 marks)

c) Add $(7)_{10}$ and $(6)_{10}$ in BCD ----- ( 2 marks)

d) Simplify (B + A)(B + D)(A + C)(C + D) ----- ( 2 marks)

e) Construct Hamming code for BCD 0110. Use even parity. -----( 2 marks)

f) Prove that " A positive logic AND operation is equivalent to a negative logic OR operation."
-----(2 marks)

g) List the applications of shift registers. ----- (2 marks)

h) Minimize the following standard POS expression using K-map Y = IIM (0,2,3,5,7) -----( 3 marks)

i) Write the entity declaration construct in VHDL for NOR gate. -----( 3 marks)


2

a) Obtain the mininal expression using Quine- Mc Cluskey method
$F(A,B,C,D)= \sum{m} (1,5,6,12,13,14) + d(2,4)$ -----(10 marks)

b) Compare TIL,CMOS and ECL families with respect to gate, voltage level, fan-in, fan-out, propagation delay, power dissipation, speed and noise margin. ----- (10 marks)


3

a) Design a logic circuit to convert BCD to Gray code ----- (10 marks)

b) Implement the following using 8:1 MUX.$F(A,B,C,D) = \sum{m} (0,1,3,5,7,10,11,13,14,15)$ ---(5 mark)

c) Explain Astable multivibrator. -----( 5 marks)


4

a) Explain Master-Slave J-K flipflop. -----( 5 marks)

b) Design 1 : 16 Demultiplexer using 1:4 demultiplexer. -----( 5 marks)

c) Explain data flow modelling and behavioural modelling in VHDL. ----- (10 marks)


5

a) Convert JK flipflop to SR flipflop and D flipflop. -----(10 marks)

b) Design mod 12 asynchronous UP counter -----( 10 marks)


6

Write short note on (any four) :-

a) Ring Counter

b) State table

c) 2- bit Magnitude comparator

d) 3 to 8 line decoder

e) Universal shift register.

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