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Explain READ and WRITE operation of 6-T SRAM cell in detail. OR Explain working of 6-T SRAM cell.
written 7.9 years ago by gravatar for hetalgosavi hetalgosavi • 1.7k •   modified 6.7 years ago

Subject: Basic VLSI Design

Topic: Semiconductor Memories

Difficulty: Medium
vlsi design
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written 6.7 years ago by gravatar for hetalgosavi hetalgosavi • 1.7k

READ operation:

  1. Assume logic 0 at node (1) i.e. V1 = 0V. Therefore, M5 and M2 are OFF and M1 & M6 are ON (linear). Therefore V1 = 0V and V2 = VDD.
  2. Word line is activated and data lines $C_C$ is pre-changed to VDD.
  3. Therefore, M3 and M4 …

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