Subject: Basic VLSI Design

Topic: Semiconductor Memories

Difficulty: Medium

READ operation:

1. Before read operation, DL is charged to VDD/2.
2. WL is activated and thus M1 turns ON.
3. If logic 1 is stored at C1, then charge is shared with C2. Therefore there is change in voltage of DL.
4. Sense amplifier senses this change and generates valid output.
5. If voltage at DL increases, the stored bit is 1. And if voltage at DL decreases, then the stored bit is 0.
6. In DRAM cell direction of voltage change determines what is stored in cell.

WRITE operation:

1. To write 0 make DL equal to 0 or to write 1 make DL equal to 1.
2. Thus WL will be activated.
3. Based on DL the capacitor C1 is either charged or discharged.
4. If C1 is charging, logic 1 is written, and if C1 is discharging logic 0 is written.

Hold operation:

The hold time “th” is defined as the longest period of time that the cell can maintain a voltage large enough to be interpreted as logic 1; the hold time is also called the retention time.

Hold time = $t_h$ = |Δt| ≈ - $C_s$ (Δ $V_S$ /IL)

Refresh operation:

To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and then rewritten. That is perform a dummy read operation after every read or write operation.

Refresh operation summary