- Before read operation, DL is charged to VDD/2.
- WL is activated and thus M1 turns ON.
- If logic 1 is stored at C1, then charge is shared with C2. Therefore there is change in voltage of DL.
- Sense amplifier senses this change and generates valid output.
- If voltage at DL increases, the stored bit is 1. And if voltage at DL decreases, then the stored bit is 0.
- In DRAM cell direction of voltage change determines what is stored in cell.
- To write 0 make DL equal to 0 or to write 1 make DL equal to 1.
- Thus WL will be activated.
- Based on DL the capacitor C1 is either charged or discharged.
- If C1 is charging, logic 1 is written, and if C1 is discharging logic 0 is written.
The hold time “th” is defined as the longest period of time that the cell can maintain a voltage large enough to be interpreted as logic 1; the hold time is also called the retention time.
Hold time = $t_h$ = |Δt| ≈ - $C_s$ (Δ $V_S$ /IL)
To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and then rewritten. That is perform a dummy read operation after every read or write operation.
Refresh operation summary