As technology is advancing majorly due to device miniaturization, the wire interconnects starts playing a vital role in determining the performance of the system.
As the device dimensions are scaled down, so are the dimension of wires scaling down.
The minimum width of the wire is scaled by factor s, but the thickness is normally not scaled.
Thus the wire capacitance scales down by a factor of 1/s. Also, length could be scaled down by a factor of s.
The wire resistance dominates the resistance of the driving logic gate and it increases with each new technology generation.
Thus to minimize an increase in global interconnect delay the cross-sectional area of global interconnects is not scaled i.e. W and H are not scaled down for global interconnects.