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Explain clock skew & describe techniques to minimize it
written 6.2 years ago by | • modified 5.1 years ago |
Subject: Basic VLSI Design
Topic: VLSI Clocking and System Design
Difficulty: Medium
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written 6.2 years ago by | • modified 5.1 years ago |
Subject: Basic VLSI Design
Topic: VLSI Clocking and System Design
Difficulty: Medium
written 5.1 years ago by |
For example, if clock transition reaches a point A on IC at time $t_a$. With respect to reference circuit and it reaches point B on IC at time $t_b$ with respect to reference to circuit then circuit skew between two points is
$t_a$ – $t_b$.