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Explain clock skew & describe techniques to minimize it

written 3.7 years ago by | • modified 2.6 years ago |

**Subject:** Basic VLSI Design

**Topic:** VLSI Clocking and System Design

**Difficulty:** Medium

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1.6kviews

Explain clock skew & describe techniques to minimize it

written 3.7 years ago by | • modified 2.6 years ago |

**Subject:** Basic VLSI Design

**Topic:** VLSI Clocking and System Design

**Difficulty:** Medium

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written 2.6 years ago by |

- The clock distribution has to be balanced so that phase of circuit (i.e. position of circuit edge with respect to reference) are different places in the system is exactly same, (i.e. phase difference is zero)
- However this is not practically achievable and results into clock skew.
- The spatial variation in clock transition time on an integrated circuit (IC) is called clock skew.
For example, if clock transition reaches a point A on IC at time $t_a$. With respect to reference circuit and it reaches point B on IC at time $t_b$ with respect to reference to circuit then circuit skew between two points is

$t_a$ – $t_b$.

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