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Basic Electronics : Question Paper Jun 2012 - First Year Engineering (C Cycle) (Semester 1) | Visveswaraya Technological University (VTU)

## Basic Electronics - Jun 2012

### First Year Engineering (C Cycle) (Semester 1)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.

1 (a) (i) Zener diode can be used for rectification. This statement is:
a) True
b) False
c) Neither true nor false
d) None of these
(1 marks)
1 (a) (ii) PIV in case of half wave rectifier for all input signal Vmsin?t is:
a) Vm
b) 2Vm
c) Vm/2
d) Vm/?2
(1 marks)
1 (a) (iii) If frequency of input is 60 Hz for a full wave rectifier, the frequency of ripple is
a) 30 Hz
b) 60 Hz
c) 120 Hz
d) 180 Hz
(1 marks)
1 (a) (iv) If a peak to peak voltage is 4V then RMS voltage is:
a) ?2 Volt
b) 2 Volt
c) 2.82 Volt
d) Both A&C
(1 marks)
1 (b) Calculate the reverse saturation current for silicon diode which passes a current of 10mA at 27°C, for a forward bias of 700mV.(4 marks) 1 (c) Explain the effect of temperature on the diode characteristics and also on the power rating of the diode.(6 marks) 1 (d) Explain the operations of a full wave center tap rectifier with neat circuit diagram and wave forms?(5 marks)

2 (a) (i) Bipolar junction transistor is a _____ controlled device.
a) Voltage
b) Current
c) Power
d) Temperature
(1 marks)
2 (a) (ii) Operating point must be _____ for proper functioning of transistor.
a) Increasing
b) Decreasing
c) Stable
d) High
(1 marks)
2 (a) (iii) The DC load line of a transistor is a:
a) Curved line
b) '-'ve slope line
c) '+' ve slope line
d) Zero slope line
(1 marks)
2 (a) (iv) In a transistor ? and ? are related by:
a) ?=1/(1-?)
b) ?=?/(1+?)
c) ?=?/(1-?)
d) ?=1/(1-?)
(1 marks)
2 (b) Explain the characteristics of common base transistor configuration with neat circuit diagram.(8 marks) 2 (c) What is a DC load line? Explain with a fixed bias circuit diagram.(4 marks) 2 (d) For the fixed bias circuit shown in the figure, VBE=0.7V, ?=60,
find:
i) Quiescent values of base and collector currents
ii) Quiescent value of VCE
iii) Base-ground and collector ground voltages
iv) Base-collector voltage
(4 marks)

3 (a) (i) In voltage divider bias circuit RE is used for:
a) Stabilization
c) As a bypass element
d) All of these
(1 marks)
3 (a) (ii) For exact analysis of voltage divider circuit _______ theorem is used
a) Norton's
b) Thevenin's
c) Superposition
d) Any one of these
(1 marks)
3 (a) (iii) _____ is the linear region of transistor characteristics.
a) Saturation
b) Cut-off
c) Active
d) Both A&C
(1 marks)
3 (a) (iv) Stability factor of fixed bias circuit is,
a) ?
b) ?-1
c) 1+?
d) None of these
(1 marks)
3 (b) List the factors which affect the stability of operating point.(4 marks) 3 (c) With a neat circuit diagram, explain voltage divider biasing circuit and derive the expression for VCE and IC using exact analysis.(8 marks) 3 (d) For the circuit shown in the figure using Silicon transistor with VBE=0.7V and ?=80, find VCE and VB (4 marks)

4 (a) (i) The device which has wide application in pulse generation is:
a) FET
b) BJT
c) Diode
d) UJT
(1 marks)
4 (a) (ii) The FET is a _____ controlled device.
a) Current
b) Voltage
c) Power
d) Temperature
(1 marks)
4 (a) (iii) The device which is known as a thyristor is:
a) Diode
b) FET
c) Transistor
d) SCR
(1 marks)
4 (a) (iv) In FET the gate source junction is:
a) Forward biased
b) Reverse biased
c) Unbiased
d) None of these
(1 marks)
4 (b) Explain the working of FET with neat circuit diagram and relevant characteristics. Indicate each region of characteristics.(8 marks) 4 (c) Explain the working of UJT with neat circuit diagram. Indicate all regions in the characteristics.(8 marks)

5 (a) (i) The coupling capacitors in RC couple amplifier affect _____ frequency response
a) Low
b) High
c) Very high
d) Above 100 kHz
(1 marks)
5 (a) (ii) The frequency at which oscillator will operate is the frequency for which the phase shift of the loop gain is:
a) 0°
b) 360°
c) 180°
d) Both A&B
(1 marks)
5 (a) (iii) In an oscillator the phase shift produced by amplifier is:
a) 0°
b) 180°
c) 90°
d) 270°
(1 marks)
5 (a) (iv) The oscillator used to generate oscillations in audio frequency range is:
a) LC oscillator
b) RC oscillator
c) Crystal oscillator
d) Both A&B
(1 marks)
5 (b) Explain the working of RC phase shift oscillator with neat circuit diagram and waveforms at each stage.(8 marks) 5 (c) List the effects of negative feedback.(4 marks) 5 (d) In a transistor Hartley oscillator, L1=10�H, L2=10�H. Find the value of C required for an oscillating frequency of 150 kHz, take M=0.(4 marks)

6 (a) (i) An op-amp has _____ output impedance.
a) ?
b) 0
c) 10000?
d) 600?
(1 marks)
6 (a) (ii) Voltage follower has _____ gain.
a) High
b) Low
c) Unity
d) None of these
(1 marks)
6 (a) (iii) An op-amp non-inverting amplifier has R1=1k & Rf=3k when Vi=2V the output is:
a) - 4V
b) 4V
c) 8V
d) - 8V
(1 marks)
6 (a) (iv) Op-amp configuration used as a buffer is:
a) Inverting amplifier
b) Non-inverting amplifier
c) Voltage follower
(1 marks)
6 (b) List the characteristics of ideal op-amp and practical op-amp.(8 marks) 6 (c) The input to the op-amp shown in the figure 6.c., at the non-inverting terminal is 10 sin10t volts. Determine the output waveform indicating time period and maximum values. (4 marks)
6 (d) Find the output of the op-amp circuit shown in figure 6.d. (4 marks)

7 (a) (i) (100)10= (?)16
a) 64
b) 144
c) 46
d) 80
(1 marks)
7 (a) (ii) 75 in binary contains _____ number of 1's.
a) 8
b) 4
c) 6
d) 3
(1 marks)
7 (a) (iii) (16)8= (?)10
a) 18
b) 20
c) 14
d) 25
(1 marks)
7 (a) (iv) (ABC)16= (?)10
a) 3000
b) 4230
c) 2748
d) 2250
(1 marks)
7 (b) Perform the following:
i) (101110)2=(?)8
ii) (110011)2-(011001)2=(?)2
iii) (E10A2)16-(5FF1)16=(?)16
iv) (77721)8-(66432)8=(?)8
v) (2384)16=(?)8
(5 marks)
7 (c) Explain the need for modulation.(5 marks) 7 (d) Explain the working of a super heterodyne receiver with neat circuit diagram and waveforms at each stage.(5 marks)

8 (a) (i) The EX-OR gate is which one input is connected to VCC, operates as _____ gate.
a) AND
b) OR
c) NOR
d) NOT
(1 marks)
8 (a) (ii) The gate whose output 1's zero only when both the inputs are high is _____ gate.
a) NAND
b) NOR
c) OR
d) AND
(1 marks)
8 (a) (iii) A+A'B+A is:
a) A
b) B
c) A+B'
d) A+B
(1 marks)
8 (a) (iv) Universal gates are:
a) NAND & NOR
b) AND & NAND
c) OR & NOR
d) NOR & EX-NOR
(1 marks)
8 (b) What is a half adder and implement it using universal gates.(6 marks) 8 (c) Simplify and realize the Boolean expression using two input NAND gates only.
i) ABCD+AB'CD
ii) AB+ABC+ABC'+A'BC
iii) ABCD+A'BCD+ABD
(10 marks)

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