Gate characteristics of SCR
1 Answer

In a thyristor, the gate is connected to the cathode through a $P N$ junction and it resembles a diode. Therefore, the $V-I$ characteristic of a gate is similar to a diode but varies considerably in units.

The circuit which supplies firing signals to the gate must be designed -

(1) to accommodate these variations

(2) not to exceed the maximum voltage, and power capabilities of the gate

(3) to prevent triggering from false signals or noise

(4) to assure desired triggering

The design specification pertaining to gate characteristics are usually provided by the manufacturer. Fig. 1 shows the gate characteristics of a typical SCR. Here, positive gate to cathode voltage $V_{g}$ and positive gate to cathode current $I_{g}$ represent d.c. values.

Applying gate drive increases the minority carrier density in the inner P layer and thereby facilitate the reverse breakdown of the junction $J_2$ . There are maximum and minimum limits for gate voltage and gate current to prevent the permanent destruction of junction $J_{3}$ and to provide reliable triggering. Similarly, there is also a limit on the maximum instantaneous gate power dissipation $\left(P_{g \max }=V_{g} I_{g}\right)$ The permissible maximum value of $P_{g m a x}$ depends on the type of gate drive. The gate signal can be DC or AC or a sequence of high frequency pulses. With pulse firing, a larger amount of instantaneous gate power-dissipation can be tolerated if the average-value of $P_{g}$ is within the permissible limits. Hence, the gate can be driven harder (greater $V_{g}$ and $I_{g} )$ when pulse firing is used. This provides for reliable and faster turm-on of the device.

All possible safe operating points for the gate are bounded by the low and high current limits for the $V-I$ characteristics, maximum gate voltage, and the hyperbola representing maximum gate power.

Within these boundaries there are three region of importance.

(1) The first region $O A$ lies near the origin (shown hatched) and is defined by the maximum gate voltage that will not trigger any device. This value is obtained at the maximum rated junction temperature (usually $125^{0}C$ ). The gate must be operated in this region whenever forward bias is applied across the thyristor and triggering is not necessary. In other words, this region sets a limit on the maximum false signals that can be tolerated in the gate-firing circuit.

(2) The second region is further defined by the minimum value of gate-voltage and current required to trigger all devices at the minimum rated junction temperature. This region contains the actual minimum firing points of all devices. In a sense, it is a forbidden region for the firing circuit because a signal in this region may not always fire all devices or never fire any at all. In Fig.1, $O L$ and $O V$ are the minimum gate-voltage and gate current limits respectively.

(3) The third region is the largest and shows the limits on the gate-signal for reliable firing. Ordinarily, a signal in the lower left part of this region is adequate for firing. For applications, where fast turn-on is required, a 'hard' firing signal in the upper right part of the region may be needed.

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In Fig.1 curves $O N$ and $O M$ corresponds to the possible spread of the characteristic for SCRs of the same rating. For best results, the operating point $S,$ which may change from $S_{1}$ to $S_{2},$ must be as close as possible to the permissible $P_{g}$ curve and must be contained within the maximum and minimum limits of gate voltage and gate current. This provides the necessary hard drive for the device.

For selecting the operating point, usually a load line of the gate voltage $E_{s}=O H$ is drawn as $H D .$ The gradient of the load line $H D(=O H / O D)$ will give the required gate source resistance $R_{g}$ . The maximum value of this series resistance is given by the line $H E$ , where E is the point of intersection of lines indicating the minimum gate voltage and gate current. The minimum value of gate source series resistance is obtained by drawing a line $H C$ tangential to $P_{g}$ curve.

A thyristor may be considered to be a charged controlled device. Thus, higher the magnitude of gate current pulse, lesser is the time needed to inject the required charge for turning on the thyristor. Therefore the SCR turn-on time can be reduced by using gate current of higher magnitude. It should be ensured that pulse width is sufficient to allow the anode current to exceed the latching current. In practice, the gate pulse width is usually taken as equal to or greater than SCR turn-on time, $t_{o n}$ . If T is the pulse width as shown in Fig.2 then $$T \geq t_{o n}$$

With pulse firing, if the frequency of firing f is known, the peak instantaneous gate power dissipation $P_{g \max }$ can be obtained as

$$ P_{g \max }=V_{g} I_{g}=\frac{P_{g_{a v}}}{f T}--------(1) $$

$\begin{array}{ll}{\text { where }} & {f=\frac{1}{T_{1}}=\text { frequency of firing or pulse repetition rate in Hz }} \\ {\text { and }} & {T=\text { pulse width in second }}\end{array}$

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A duty cycle is defined as the ratio of pulse-on period to the periodic time of pulse. In the Fig.2 pulse-on period is T and the periodic time is $T_{1} .$ Therefore, duty-cycle is given by $$\delta=\frac{T}{T_{1}}=f T---------(2)$$

From Eq. $(1)$

$$ \frac{P_{g_{av}}}{\delta} \leq P_{g \max } $$

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