Subject :- VLSI Design

Topic :- VLSI Clocking and System Design

Difficulty :- Medium

    Library ieee;
         use ieee_std_logic_1164.all;

    entity mux4to1 is
        port( A,B,C,D: in std_logic; 
        S: in std_logic_vector(1 downto 0); 
         O: out std_logic); 

    end mux4to1:

    Architecture behavioral of mux4to1 is  

    Begin  
          Process(S,A,B,C,D) 
        variable temp : std_logic;   // variable declaration  

 Begin    
        if(S="00")then    
        temp:=A
   elsif(S="01")then   // note that it is 'elsif' not 'else if' of C

    temp:=B; 
        elsif(S="10")then   

    temp:=C;       
        else

    temp:=D; 
        end if;           // used to terminate the if statement  

    O<=temp;         // passing on the value of the variable  
        end Process;   
        end behavioral;