Subject :- VLSI Design

Topic :- VLSI Clocking and System Design

Difficulty :- Medium

library ieee;                
 use ieee_std_logic_1164.all;      

  entity dff IS                     
         Port( data :in std_logic ;                  
         clk: in std_logic ;                
         q: out std_logic ;                      
               );           
        End dff;             

 architecture dff_a of dff IS            
        begin             
       Process(clk)              
       begin             
       If (clk event and clk =’1’ ) then            
       q<= data ;             
       End if;         
      End process ;           
      End dff_a;

***D Flip flop with Synchronous,Reset,Set and clock enable***
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity example_FDRSE is 

   port(
      Q : out std_logic;      -- Data output
      CLK :in std_logic;      -- Clock input
      CE :in std_logic;    -- Clock enable input
      RESET :in std_logic;  -- Synchronous reset input
      D :in  std_logic;      -- Data input
      SET …