Subject :- VLSI Design

Topic :- VLSI Clocking and System Design

Difficulty :- Medium

Library ieee:                  
Use ieee. Std_logic_1164.all                       
Entity barrel_shifter is                  
Port( D3, D2, D1, D0: In std_logic;               
         Sel1, sel0: In std_logic;               
          Y3, Y2,Y1,Y0: out std_logic;                     
           );                     
End barrel_shift:           

Architecture struct_a of barrel_shif is            
Component my_mux4            
Port(i0,i1,i2,i3: In std_logic ;               
     S1, S0 : In std_logic ;              
      Y In std_logic ;              
           );              
End component;             

Begin                   
U1: my_mux4 port map(i0=>D3,i1=>D2,i2=>D1,i3=>D0, S1=>Sel1,S0=>Sel0,Y=>Y3);             
U2: my_mux4 port map(i0=>D0,i1=>D3,i2=>D3,i3=>D3, S1=>Sel1,S0=>Sel0,Y=>Y2);              
U3: my_mux4 port map(i0=>D1,i1=>D2,i2=>D0,i3=>D0, S1=>Sel1,S0=>Sel0,Y=>Y1);              
U4: my_mux4 port map(i0=>D2,i1=>D2,i2=>D1,i3=>D1, S1=>Sel1,S0=>Sel0,Y=>Y0);                
End struct_a;