Subject :- VLSI Design

Topic :- Data Path Design

Difficulty :- High

Clocked D Flip Flop

Figure shows the Clocked Flip flop with additional two and gates with two inputs are clock and D. When the clock is low it disables the two AND gates and prevents the Flip flop from changing the states.

When a clock is high, it is important as the flip flop output state depends on the input D bit. A high D sets the flip flop output high and a low D resets it.

Based on the input clock triggering mechanism the d flip flops are divided as level triggered and edge triggered flip flops.

D flip flop Truth table