Question: How low power circuit is designed through voltage scaling
0

Subject :- VLSI Design

Topic :- Semiconductor Memories

Difficulty :- Low

cmos(48) • 693 views
ADD COMMENTlink
modified 14 months ago by gravatar for Sanket Shingote Sanket Shingote250 written 16 months ago by gravatar for awari.swati831 awari.swati831250
0

A simple formula is proposed for the analysis of the gate delay of CMOS gate under low V/sub DD/. The effects of device parameters on gate delay and energy are readily obtained using the formula. Thus, it has the potential for use in the design of device parameters in the low V/sub DD/ CMOS circuits.

Is Power Really A Problem?

  • Scaling of technology node increases power-density more than expected. CMOS technology beyond 65nm node represents a real challenge for any sort of voltage and frequency scaling Starting from 120nm node, each new process has inherently higher dynamic and leakage current density with minimal improvement in speed. Between 90nm to 65nm the dynamic power dissipation is almost same whereas there is ~5% higher leakage/mm2.Low cost always continues to drive higher levels of integration, whereas low cost technological breakthroughs to keep power under control are getting very scarce.

  • Modern System-on-Chip demand for more power. In both logic and memory, Static power is growing really fast and Dynamic power kind of grows. Overall power is dramatically increasing. If the semiconductor integration continue to follow Moore's Law, the power density inside the chips will reach far higher than the rocket nozzle.

Do We Need To Bother With Power?

  • Power dissipation is the main constrain when it comes to Portability. The mobile device consumer demands more features and extended battery life at a lower cost. About 70% of users demand longer talk and stand-by time as primary mobile phone feature. Top 3G requirement for operators is power efficiency. Customers want smaller & sleeker mobile devices. This requires high levels of Silicon integration in advanced processes, but advanced processes have inherently higher leakage current. So there is a need to bother more on reducing leakage current to reduce power consumption.

• Why Power Matters in SOC?

Power Management matter in System on Chip due to following concerns

a)Packaging and Cooling costs.
b)Digital noise immunity,
c)Battery life (in portable systems)
d)Environmental concerns.

  • The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage. Therefore, reduction of $V_{DD}$ emerges as a very effective means of limiting the power consumption. Given a certain technology, the circuit designer may utilize on chip DC- DC converters and/or separate power pins to achieve this goal. The savings in power dissipation comes at a significant cost in terms of increased circuit delay. When considering drastic reduction of the power supply voltage below the new standard of 3.3 V, the issue of time domain performance should also be addressed carefully. Reduction of the power supply voltage with a corresponding scaling of threshold voltages, in order to compensate for the speed degradation.

  • Influence of Voltage Scaling on Power and Delay Although the reduction of power supply voltage significantly reduces the dynamic power dissipation, the inevitable design tradeoff is the increase of delay. This can be seen easily by examining the following propagation delay expressions for the CMOS inverter circuit, he dependence of circuit speed on the power supply voltage may also influence the relationship between the dynamic power dissipation and the supply voltage. The above equation suggests a quadratic improvement (reduction) of power consumption as the power supply voltage is reduced.

  • However, this interpretation assumes that the switching frequency (i.e., the number of switching events per unit time) remains constant. If the circuit is always operated at the maximum frequency allowed by its propagation delay, the number of switching events per unit time (i.e., the operating frequency) will drop as the propagation delay becomes larger with the reduction of the power supply voltage. The net result is that the dependence of switching power dissipation on the power supply voltage becomes stronger than a simple quadratic relationship, shown in Figure: It is important to note that the voltage scaling is distinctly different from constant-field scaling , where the power supply voltage as well as the critical device dimensions (channel length, gate oxide thickness) and doping densities are scaled by the same factor.

  • Here, we examine the effects of reducing the power supply voltage for a given technology, hence, key device parameters and the load capacitances are assumed to be constant. The propagation delay expressions show that the negative effect of reducing the power supply voltage upon delay can be compensated for, if the threshold voltage of the transistors ($V_{T}$) is scaled down accordingly. However, this approach is limited because the threshold voltage may not be scaled to the same extent as the supply voltage. When scaled linearly, reduced threshold voltages allow the circuit to produce the same speed-performance at a lower $V_{DD}$. Figure shows the variation of the propagation delay of a CMOS inverter as a function of the power supply voltage, and for different threshold voltage values.

    $\tau_{PLH}=\frac{C_{load}}{k_p(V_{DD}-V_{T,P})}\Big[\frac{2V_{T,P}}{V_{DD}-V_{T,P}} + ln \Big( \frac{4(V_{DD}-V_{T,P})}{V_{DD}} -1 \Big) \Big]$

    $\tau_{PLH}=\frac{C_{load}}{k_p(V_{DD}-\begin{vmatrix}V_{T,P}\end{vmatrix})}\Big[\frac{2\begin{vmatrix}V_{T,P}\end{vmatrix}}{V_{DD}-\begin{vmatrix}V_{T,P}\end{vmatrix}} + ln \Big( \frac{4(V_{DD}-\begin{vmatrix}V_{T,P}\end{vmatrix})}{V_{DD}} -1 \Big) \Big]$

enter image description here

Scheme (SATS).

  • The variable-threshold CMOS circuit design techniques are very effective for reducing the sub threshold leakage currents and for controlling threshold voltage values in low $V_{DD}$ - low $V_T$ applications. However, this technique usually requires twin-well or triple-well CMOS technology in order to apply different substrate bias voltages to different parts of the chip. Also, separate power pins may be required if the substrate bias voltage levels are not generated onchip. The additional area occupied by the substrate bias control circuitry is usually negligible compared to the overall chip area.

enter image description here

  • The internal supply voltage is generated on-chip, by a DC-DC converter circuit. circuits of the chip usually operate with a higher external supply voltage, in order to increase the noise margins and to enable communication with the peripheral devices. An on-chip DC-DC voltage converter generates the low internal supply voltage $V_{DDL}$, which is used by the internal circuitry. Two signal swing converters (level converters) are used to reduce the voltage swing of the incoming input signals, and to increase the voltage swing of the outgoing output signals, respectively. The internal low-voltage circuitry can be designed using VTCMOS techniques, where the threshold voltage control unit adjust the substrate bias in order to suppress leakage currents.

    $dealy=constant\frac{C_L}{V_{DD}[1-\frac{V_T}{V_{DD}}]^2}$

  • Threshold voltage can be scaled down to get the same performance, but it may increase the concern about the leakage current and noise margin.

ADD COMMENTlink
modified 15 months ago by gravatar for Sanket Shingote Sanket Shingote250 written 15 months ago by gravatar for dukare030296hemant dukare030296hemant90
Please log in to add an answer.