Question: Show realization of MOSFET based on Bit Shift Register

Subject :- VLSI Design

Topic :- MOS Circuit Design Styles

Difficulty :- Medium

cmos(48) • 796 views
modified 14 months ago by gravatar for Sanket Shingote Sanket Shingote250 written 16 months ago by gravatar for awari.swati831 awari.swati831250

The Shift registers are normally having group of flip-flops. Flip-flop is a 1 bit memory cell. In shift register the flip-flops are controlled by the clock. The number of flip-flops in shift register represent the number of bits used in it. When clock pulse is high data bit is enter into the first flip-flop in the shift register and the data is shifted to the other flip-flop during each clock pulse. The shifting is done by two ways, one is serial shifting and another one is parallel shifting. The following fig.1 shows the master slave flip-flop and based shift register.

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The following fig.2 represents the one of the flip- flop model namely Power PC Style(PPCFF). It is fastest and high quality structure and have a short direct path and low power clock load.

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Registers Numbers of gate used Delay(ns) Power ($\mu$ W) Power delay product(J) ($*e^{-15}$)
SISO 8 0.338 2.221 0.7506
SIPO 12 0.38(Q1), 20.38(Q2), 40.38(Q3), 60.34(Q4) 2.221 0.8439, 45.2339, 89.6839, 134.015
PISO 12 0.340 3.1 1.054
PIPO 8 0.338(Q1), 0.338(Q2), 0.338(Q3), 0.338(Q4) 2.91 0.9835, 0.9835, 0.9835, 0.9835
written 15 months ago by gravatar for dukare030296hemant dukare030296hemant90
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