Explain the pseudo NMOS logic with suitable example
1 Answer
  • The inverter that uses a p-device pull-up or load that has its gate permanently ground. An n-device pull-down or driver is driven with the input signal. This roughly equivalent to use of a depletion load is Nmos technology and is thus called ‘Pseudo-NMOS’.

  • The circuit is used in a variety of CMOS logic circuits. In this, PMOS for most of the time will be linear region. So resistance is low and hence RC time constant is low. When the driver is turned on a constant DC current flows in the circuit.

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The CMOS pull up network is replaced by a single pMOS transistor with its gate grounded. Since the pMOS is not driven by signals, it is always ‘on'. The effective gate voltage seen by the pMOS transistor is $V_{DD}$. Thus the overvoltage on the p channel gate is always $V_{DD} -V_{TP}$. When the nMOS is turned ‘on', a direct path between supply and ground exists and static power will be drawn. However, the dynamic power is reduced due to lower capacitive loading.

  • We design the basic inverter and then scale device sizes based on the logic function being designed.
  • The load device size is calculated from the rise time.
    $\tau_{rise}=\frac{C}{K_p(V_{DD} -V_{TP})}[\frac{2V_{Tp}}{V_{DD} -V_{TP}}+ln\frac{V_{DD}+V_{oH} -2V_{TP}}{V_{DD} -V_{oH}}]$
  • Given a value of $\tau_{rise}$, operating voltages and technological constant, $K_p$ and hence, the geometry of the p channel transistor can be determined.
  • Geometry of the n channel transistor can be determined from static considerations.
  • We take $V_{oL}=V_{Tn},$ and calculate $\beta$
  • But $\beta=K_n/K_p \,and \,K_p$ is already known.
  • This evaluates $K_n$ and hence, the geometry of the n channel transistor.
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