• 2 stage opamps are used when the output voltage swing must be maximised.
• As shown in figure, we can identify 3 poles,
  
  • at X (or Y)
  • at E (or F)
  • at A (or B)
• Pole X lies at relatively high frequencies.
• At node A, the small signal resistance is lower bu the value of $C_L$ may be quite high.
• Therefore circuit exhibits 2 dominant poles.

• In bode plot,(fig:b)

$\omega_{P,E}$ -assumed more dominant
$\hspace{1cm}$- but relative positions of $\omega_{P,E}$ & $\omega_{P,A}$
$\hspace{1cm}$ depends on design and load capacitance.

• Since, the plots at 'E' & 'A' are relatively close to origin, the phase approaches -$180^0$ well below 3rd pole.
  Therefore,PM=>quite close to zero.

• One of the dominant poles must be moved towards origin so as to place the gain cross over well below phase crossover.

• However, the unity gain BW after compensation cannot exceed the frequency of 2nd pole of the open loop system.

• Thus if the magnitude of $\omega_{P,E}$ is decreasing, the available BW is limited to approx, $\omega_{P,A}$ a low value.

• Furthermore, the very small magnitude of the required dominant pole translates to a very large compensation capacitor.

• In fig:(c)

• It can be observed that the 1st stage- exhibited high output impedance & 2nd stage provides moderate gain, thereby providing suitable environment for Miller multiplication of capacitors.

• The idea is to create large capacitance at node 'E' equal to $(1+A_{v2})C_C$ moving the corresponding pole to
  $\hspace{3cm} R_{out}^{-1}\Big[ C_E+(1+A_{v2})C_C \Big]^{-1}$
  $\hspace{2cm} $ where, $C_E$ -> capacitance at node E before adding $C_C$.

• As a result, a low frequency pole can be established with a moderate capacitance value, saving considerable chip area.