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Single ended signaling & differential ended signalling
written 6.1 years ago by | • modified 2.3 years ago |
Subject: CMOS VLSI Design
Topic: Differential Amplifiers
Difficulty: Medium
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written 6.1 years ago by | • modified 2.3 years ago |
Subject: CMOS VLSI Design
Topic: Differential Amplifiers
Difficulty: Medium
written 6.1 years ago by | • modified 6.1 years ago |
i) An important advantage of differential signalling over single ended signalling is higher immunity to environmental noise.
ii) Consider fig:(a)
Clock line- carries a large clock signal.
Signal line- carries small sensitive signal.
Due to capacitive coupling between two lines, transitions on clock line may corrupt signals on signal line. …