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Draw and explain LC oscillator.

Subject: CMOS VLSI Design

Topic: Mixed Signal Circuits

Difficulty: Medium

cvd • 1.6k  views
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i) LC ocsillations is biased at a drain current of $I_1$, if the series resistance of $L_P$ is small, the dc level of $V_{out}$ is close to $V_{DD}$.
$V_{out}$ is an inverted sinusoid with an average value near $V_{DD}$ because the inductor cannot sustain a large dc drop.

ii) In other words, if the average value of $V_{out}$ deviates significantly from $V_{DD}$, then the inductor series resistance must carry the average current greater than I. Thus the peak output level infact exceed the supply voltage, an important and often useful attribute of the LC load with proper design the output peak to peak swing can be longer than $V_{DD}$.

iii) Frequency of oscillations= $\omega_1= \frac{1}{\sqrt{C_P,\,L_P}}$