Digital Circuits and Design - December 2015

MU Electronics Engineering (Semester 3)

Total marks: --
Total time: -- INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary 1 (a) Explain drawback of synchronous counter. 5 marks

1 (b) Differentiate synchronous and asynchronous counter. 5 marks

1 (c) Draw truth table and logical diagram of half adder. 5 marks

1 (d) Explain Fan in, Fan out, power dissipation and noise immunity with reference to digital Ics. 5 marks

2 (a) Design MOD 12 asynchronous counter using T flip flop. 5 marks

2 (b) Discuss Xilinx XC 9500 CPLD architecture. 5 marks

3 (a) Design MOD-60 counter using IC 74163. 5 marks

3 (b) Analyze the sequential state machine shown in figure. Obtain state diagram for the same.
5 marks

4 (a) Simplify following logic function and realize using NAND gate
(i) F=1:m (1, 2, 4, 7, 10, 11, 13)+ d(9, 15)
(ii) F=2:m (1, 2, 3, 5, 8, 9, 11, 13, 15) + d(6). 5 marks

4 (b) Design a Mealy type sequence detector to detect a serial input sequence of 101. 5 marks

5 (a) Draw a circuit diagram of two input TTL NAND gate and explain its operation. 5 marks

5 (b) Design 4 bit Johnson counter using J-K Flip Flop. Explain it operation using waveform. 5 marks

Write a short note on.

6 (b) Multiplexers 5 marks

6 (c) Noise Margin. 5 marks