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Digital Electronics & Logic Design Question Paper - May 2017 - Information Technology (Semester 3) - Savitribai Phule Pune University (SPPU)

## Digital Electronics & Logic Design - May 2017

### SPPU Information Technology (Semester 3)

Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary
1(b) Implement the following Boolean function using single 8:1 multiplexer:
F (A, B, C, D) = ∑m(1, 4, 6, 9, 13)
6 marks

2(a) Do the folllowing
i) (7F)16 - (5C)16 using 2's complement method
ii) (735.25)10 = (?)16
iii) (101011.111011)2 = (?)8 (?)16
6 marks

2(b) Simplify the following Boolean function using Quine MC-Clusky Technique F (A, B, C, D) = ∑(0, 3, 7, 8, 9, 11, 15). 6 marks

### Solve any one question from Q.3(a,b) &Q.4(a,b)

3(a) Desing and draw logic diagram of mod 45 counter using IC 7490 6 marks

3(b) Design sequence gernerator to genertae the sequence 1011 using shift register IC 74194. 6 marks

4(a) Explain with a neat diagram Ring Counter. 6 marks

4(b) Design flip-flop conversion logic to convert JK flip-flop to T flip-flop. 6 marks

### Solve any one question from Q.5(a,b) &Q.6(a,b)

5(a) Draw the ASM chart for 2-bit binary Up/ Down counter with control input M such that if M =0 counter counts in Up direction and if M=1 Counter counts in Down Direction. Design the same using MUX Controller Method using D flip-flops. 6 marks

5(b) Explain architecture of CPLD with the help of suitable diagram. 6 marks

6(a) Design Full Adder using PLA. 6 marks

6(b) Compare CPLD and FPGA 6 marks

### Solve any one question from Q.7(a,b) &Q.8(a,b)

7(a) Explain VHDL modeling styles with example. 6 marks

7(b) Write VHDL program for 3:8 decoder. 6 marks

8(a) What is VHDL? Write features of VHDL Explain the structure of VHDL module. Define entity and architecture for 2 input OR gate. 6 marks

8(b) Explain the difference between concurrent and sequential statement with an example. 6 marks

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