Serial Interface Bus

1. It is developed by Motorola.
2. Protocol used is synchronous bus, full duplex, bidirectional.
3. Multiple masters can be used but, only one master is active at a time.

4. It has 4 wire bus i.e. It uses four wires i.e. 4 signals lines - SCLK, MOSI, MISO & (SS) ̅

   • SCLK – serial clock – Signal line carrying clock signal.
   • MISO – Master In Slave Out – Signal line carrying data from master to slave device.
   • MOSI – Master Out Slave In – Signal line carrying data from slave to master device.
   • (SS) ̅ – Slave Select (active low) – Signal line for slave device select.

5. Master device provides clock to slave devices. Also select slave devices by enabling (SS) ̅ pin.

6. MISO of other slave devices will be at high impedance state.
7. Serial peripheral control register holds various configuration parameters. Status register holds status of various conditions for transmission and reception.
8. The principle of working is as shift register. Master and slave contain shift registers where sizes are device dependent.
9. Data in Master Shift register is shifted out to MOSI and enters the shift register of slave device through MOSI of slave. Output from the slave enters the master through MISO.
10. Shift register from master and slave forms Circular Buffer.
11. SPI do not support acknowledgement mechanism.
12. Speed is up to 4 mbps.
13. It is commonly used for high speed communication between microcontroller peripherals like EEPROMs, data converters and display drivers.

14. Interfacing diagram is given as follows -

    

Parallel Interface Bus

1. It is used for communicating with peripheral devices which are memory mapped to host of the system.
2. Host has a parallel bus and control over read/ write.
3. Communication through parallel bus is controlled by control signal interface between host and device.
4. Control Signals are read or write signals and device select signals.
5. Device becomes active by selecting host processor.
6. Direction of data transfer are controlled through control signal lines for ‘read’ and ‘write’.
7. An address decoder circuit is used for generating chip select signal for the device.
8. When the address selected is in the range, chip select line is activated by decoder circuit.
9. If device wants to start communication, it can inform the same to processor through interrupts.

10. Parallel data communication offers highest speed for data transfer.