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State the Digital design using Verilog/ VHDL: Advantages and disadvantages.
written 7.4 years ago by gravatar for hetalgosavi hetalgosavi • 1.7k modified 3.9 years ago by gravatar for pedsangini276 pedsangini276 • 4.8k

Subject : Embedded Systems Design

Topic : Embedded Hardware and Design

Difficulty level : Low
embedded systems
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written 7.4 years ago by gravatar for hetalgosavi hetalgosavi • 1.7k

Advantages:

  • Does not provide specialized language features for accessing common device features.
  • It is an excellent tool for designing lockets with PLD.
  • It provides high level language construct to describe large circuits or systems.
  • The designs and models can be stored as library.
  • The language is portable between simulation and …

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