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State the Digital design using Verilog/ VHDL: Advantages and disadvantages.

Subject : Embedded Systems Design

Topic : Embedded Hardware and Design

Difficulty level : Low

1 Answer
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Advantages:

  • Does not provide specialized language features for accessing common device features.
  • It is an excellent tool for designing lockets with PLD.
  • It provides high level language construct to describe large circuits or systems.
  • The designs and models can be stored as library.
  • The language is portable between simulation and synthesis tool.
  • Design is device independent. There is a smooth translation of design from PLD to ASIC.
  • Decrease in efficiency of designer.

Disadvantages

  • The control logic is designed with traditional techniques.
  • The intent of design gets lost in complexity and details.
  • The schematics are accompanied with documentation.
  • Portability is an issue.
  • Simulation environment for schematic capture design is not same.
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