Salient features of 8086 Microprocessor and Architecture of 8086 Microprocessor. OR Distinguish between BIU and EU of 8086 OR Explain pipeline concept used in 8086 Microprocessor.
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  1. Single +5V power supply
  2. Clock speed range of 5-10MHz
  3. capable of executing about 0.33 MIPS (Millions instructions per second)
  4. It is 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing.
  5. It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.
  6. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
  7. It has 256 interrupts.

Architecture of 8086

he following diagram depicts the architecture of a 8086 Microprocessor −

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8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface Unit).

EU (Execution Unit) Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has no direct connection with system buses as shown in the above figure, it performs operations over data through BIU.

functional parts of 8086 microprocessors.

ALU It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

BIU (Bus Interface Unit) BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory. EU has no direction connection with System Buses so this is possible with the BIU. EU and BIU are connected with the Internal Bus.

It has the following functional parts −

Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions and stores them in the instruction queue. When EU executes instructions and is ready for its next instruction, then it simply reads the instruction from this instruction queue resulting in increased execution speed.

Fetching the next instruction while the current instruction executes is called pipelining.

Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer register IP, which holds the address of the next instruction to executed by the EU.

CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.

DS − It stands for Data Segment. It consists of data used by the program andis accessed in the data segment by an offset address or the content of other register that holds the offset address.

SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.

ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra destination data.

Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be executed.

Concept of Pipelining

fetching the next instruction while the current instruction executes is known as pipelining

to speed up program execution, the bus interface unit fatches as many as 6 instruction bytes ahead of time from the memory and these are held for execution unit in the (FIFO) group of registers called QUEUE.

The BIU can fetch instruction byte while EU is decoding or executing an instruction which does not require the use of buses. When is EU is ready for the next instruction, it simply reads the instruction from queue in the BIU.

the Queue is fellied when at least two bytes are empty as 8086 has a 16 bit data bus

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