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Design a two bit magnitude comparator circuit using gates OR Implement 2 bit comparator using active low decoder

OR

A and B are the two 2 bit input to the comparator for the following condition:

1$.A=B $

2.$A\lt B $

3.$ A \gt B$

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2-bit comparator

Similarly, we can have a 2-bit comparator and the table to list all the combinations at the input and their corresponding outputs is as

1

And we get the equations for all three outputs from the K-maps as

2

We can also obtain these equations orally as for$ A_1A_0$ to be greater than $B_1B_0$ either $A_1$ is greater than$ B_1 (i.e. A_1=1 and B_1=0) or A_1$ is equal to $B_1$ (or $A_1$is not less than $B_1$i.e. $(f(A_1 \lt B_1))’ = (A_1’B_1)’= (A_1 + B_1‘) and A_0$ is greater than $B_0 (i.e. A_0=1 and B_0=0)$.

Hence the equation we get is $ f (A \gt B) = A_1B_1‘+ (A_1 + B_1’) A_0B_0’ = A_1B_1‘+ A_0B_1’B_0’+ A_1A_0B_0’$

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