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Draw the truth table & excitation table for S-R Flip flop (4m)

written 7.2 years ago by teamques10 ★ 70k

modified 5.1 years ago by akshaysainianil • 0

digital logic design

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written 7.2 years ago by teamques10 ★ 70k

SR Flipflop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates. These flip flops are also called S-R Latch.

Truth Table

S	R	Q(t+1)
0	0	Q(t)
0	1	0
1	0	1
1	1	Invalid inputs

Characteristic Equation

Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0

Excitation Table

Q(t)	Q(t+1)	S	R
0	0	0	x
0	1	1	0
1	0	0	1
1	1	x	0

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