Advantages of VHDL :

i. Executable specification

ii. Validate spec in system context (Subcontract)

iii. Functionality separated from implementation

iv. Simulate early and fast (Manage complexity)

v. Explore design alternatives

vi. Get feedback (Produce better designs)

vii. Automatic synthesis and test generation (ATPG for ASICs)

viii. Increase productivity (Shorten time-to-market) …