Subject: Logic Design

Topic: VHLD (VHSIC Hardware Description Language)

Difficulty: Medium

A standard VHDL code is composed of at least three fundamental sections

• Library Declaration:

It contains a list of all the library files to be included in the program header.

Syntax:

LIBRARY library_name;

USE library-name _ package-name. package-parts;

• Entity:

This section specifies the name of the entity, ports of the entity, and entity related information.

Entity is description of the interface between a design and external environment.

Each entity has its own architecture statement.

Syntax:

   ENTITY entity_name IS

   PORT (port_name : MODE port_type);

   END [entity_name];

• Architecture:

It contains the VHDL code which describes how the circuit should behave. Architecture describes internal organization and operations of the entity. Architecture is used to describe behavior, data flow of the design entity.

Syntax:

ARCHITECTURE arch_name OF entity_name IS

{Block declarations}

BEGIN

{Concurrent statements}

END [arch_name];