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VHDL program format ?
vhdl program format • 952  views
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VHDL stands for Very high speed integrated circuit Hardware Description Language

  • VHDL is not case sensitive
  • VHDL is a free form language.
  • You can write the whole program on a single line.

A standard VHDL code is composed of at least three fundamental sections

• Library Declaration: It contains a list of all the library files to be included in the program header.

Syntax:

LIBRARY library_name;
USE library-name _ package-name. package-parts;

• Entity:

  • This section specifies the name of the entity, ports of the entity, and entity related information.
  • Entity is description of the interface between a design and external environment.
  • Each entity has its own architecture statement.

Syntax:

 ENTITY entity_name IS

 PORT (port_name : MODE port_type);

 END [entity_name];

• Architecture:

It contains the VHDL code which describes how the circuit should behave. Architecture describes internal organization and operations of the entity. Architecture is used to describe behavior, data flow of the design entity.

Syntax:

ARCHITECTURE arch_name OF entity_name IS

{Block declarations}

BEGIN

{Concurrent statements}

END [arch_name];
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