Question: Architecture of TMS320C6XX DSP Processor
architecture of dsp • 1.2k views
modified 10 days ago by gravatar for Abhishek Tiwari Abhishek Tiwari ♦♦ 50 written 12 months ago by gravatar for Mayank Aggarwal Mayank Aggarwal20

•TMS 320C67 X is Fixed as well as Floating point processor. Central Processing Unit consists of 8 functional units. These functional units are divided into two sides A and B. The Architecture of TMS 320C67 X is shown in figure below.

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•Each side contains units M, L, S and D. These units are basically used to perform various operations; certain instruction can be executed by using more than one unit for example Add instruction. Each side contains sixteen 32 bit registers interaction with CPU is done using these registers.

•Internal buses consists of following:

i. 32-bit program address bus.

ii. 256-bit data program bus.

iii. To load data buses LD1 and LD2.

iv. Two 32-bit store data buses namely ST1 and ST2.

v. A 32-bit Direct Memory Access (DMA) data bus and 32-Bit DMA address bus.

vi. External memory is accessed through a bit 20-Bit address bus and 32-Bit data bus.

The peripheral on C6 X processes are as follows:

1.EDMA (Enhanced Direct Memory Access): It has 16 Programmable channels and RAM space to hold multiple configurations. It makes the movement of data from one place in memory to the other place without interfering with CPU operation.

2.Boot Loader: It boots the code from HPI to internal memory. It is basically used to determine what actions the DSP performs; when the device is reset.

3.McBSP (Multichannel Buffered Serial Port): It provides high speed multi-channel serial communication link. This port can buffer serial samples in memory automatically with the help of a EDMA controller. It is also having multichannel capability which is compatible with various networking standards.

4.HPI (Host Port Interference): It allows the host to access internal memory. The host and CPU can exchange the data via internal memory.

5.Time and Power down unit: Two 32-Bit general purpose timer and used to time events, count events, general pulses, interrupt the CPU etc. This unit also sends synchronization event to DMA controller. Power down unit is used to save the power for duration when CPU is inactive.

6.EMI (External Memory Interface): This block supports an interface to several external devices, like synchronous burst, asynchronous devices, external shared memory device.

written 12 months ago by gravatar for Mayank Aggarwal Mayank Aggarwal20
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