It is a multiprocessor mode. Along with 8086, there can be other processors like 8087 and 8089 in the circuit. Here MN/¯MX is connected to ground itself.
Since, there are multiple processors; ALE for the latch is given by 8288 bus controller. Instead of 8086 control signals are generated by bus controller 8288 using special decoding of status pins ¯(S0,) ¯(S1,) ¯S2.
Since 8288 independently generates control signals, it needs a CLK from 8284 clock generator.