Question Paper: Logic Design Question Paper - May 18 - Information Technology (Semester 3) - Mumbai University (MU)

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## Logic Design - May 18

### Information Technology (Semester 3)

Total marks: 80

Total time: 3 Hours
INSTRUCTIONS

(1) Question 1 is compulsory.

(2) Attempt any **three** from the remaining questions.

(3) Draw neat diagrams wherever necessary.

Q1) Solve any four out of five.

**1(a)**Explain Input and Output characteristics of CE configuration of BJT.

**1(b)**Convert following decimal number to Binary, Octal, Hexadecimal and Gray code $(154)_{10}$

**1(c)**Design EX-OR gate using only NOR gates.

**1(d)**Draw two truth tables illutstrating the outputs of a full-adder, one table for the sum output.

**1(e)**Convert S-R flip-flop to D flip-flop.

**2(a)**Implement following using only one 8:1 Multiplexer and few gates:

$$f(A, B, C, D) = \sum m (1,2,3,5,6,9,10,11,14)$$

**2(b)**Using Quine McCluskey Method determine Minimal SOP form for

$$ f(A, B, C, D) = \sum m (1,3,5,6,8,9,12,14,15) + \sum d (4,10,13) $$

**3(a)**Explain Collector to base bias circuit with its stability factor.

**3(b)**With neat diagram explain operation of ALU IC74181

**4(a)**Design a Mod 10 synchronous counter using S-R Flip flop.

**4(b)**Minimize the following four variable logic function using K-map:

$$ f(A, B, C, D) = \sum m (0,2,3,5,6,7,8,10,11,14,15) $$

and design using only NAND gates.

**5(a)**Simplify following equation using Boolean algebra and Design using basic gates

$$ f(A, B, C) = A'B + BC' + BC + AB'C' $$

**5(b)**Explain entiry in VHDL and write VHDL program for half subractor circuit.

Q6) Solve the following (Any Four):

**6(a)**Explain working of Universal shift register.

**6(b)**Working of T flip flop.

**6(c)**Explain working of Differential Amplifier.

**6(d)**Write VHDL program for EX-NOR gate.

**6(e)**Explain working of Encoder and Decoder.