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What are drawbacks of delta modulator and how are they overcome by ADM
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Step size is not constant.

Rather when the slope over load occurs the step size becomes progressive larger and ∴ x(+) will catch up with x(+) more rapidly.

The step size is adaptive as per level of i/p signal.

If compared with linear delta modulator, then you will find that except for the counter being replaced by digital processor, removing blocks are identical.

And $S_o (t)=-1 if x(t) \lt x’(t)$ just before kth clock edge.

Then step size at sampling instant k is :-

$S(k) = [δ(k-1)] S_o (k)+δ S_o (k-1)$

Eg : -

$k-1=5 \\ δ (k-1)= δ (5) = δ \\ δ(k-1)=δ(5)= +1$

Substituting : $- δ (6) = δ + δ = 2 δ$

∴ step size of 6th clock edge $= 2 δ%\$