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SEM- III COMP DLDA MAY 2018

(3 hours) $\hspace{70mm}$ [Max. Marks 80]

1. Question no. 1 is compulsory.

2. Assume suitable data if necessary.

3. Attempt any three questions from remaining questions.

Q.1 Answer the following questions: (20)

(a) Write the entity declaration in VHDL for NOR gate.

(b) Add (22)$_{10}$ to (56)$_{10}$ in BCD.

(c) Convert decimal 57 into binary, base 7 and hexadecimal.

(d) Construct hamming code for 1010.

(e) Perform subtraction using 2's complement for (10)$_{10}$-(7)$_{10}$.

(f) State and prove DE Morgan's law.

(g) Convert (77)$_{10}$ into Excess-3 code.

(h) Perform addition of (34)$_{8}$ and (301)$_{8}$

(i) Find 8's complement of the numbers (37)$_{8}$ and (301)$_{8}$

(j) Explain ASCII code in brief.

Q.2

(a) Simplify the following equation using k map to obtain SOP equation and realize the $\hspace{20mm}$ (10)

minimum equation using only NAND gates.

F (A, B, C, D) =$\Sigma$m (1, 2, 4, 6, 9, 10, 12, 14) + d (3, 7, 13)

(b) Implement full adder using 8:1 mux. (10)

Q.3

(a) Obtain the minimal expression using Quine Mc- Cluskey method. (10)

F (A, B, C, D) =$\Sigma$m (1, 2, 3, 5, 6, 10, 11, 13, 14) + d (4, 7)

(b) What is race around condition? How to overcome it? (10)

Q.4

(a) Design 3-bit asynchronous counter and draw the timing diagram. (10)

(b) Convert JK flip-flop to SR flip-flop and D flip-flop. (10)

Q.5

(a) Compare TTL and CMOS with respect to different parameters. (10)

(b) Explain the features of VHDL and its modelling styles. (10)

Q.6 Write short notes on any four. (20)

(a) Moore and Mealy machine

(b) Sequence generator

(c) Universal shift register

(d) Priority encoder

(e) Carry look ahead adder

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