Pipeline Depth: 3 stage (Fetch, Decode, Execute)

1. Operating frequency: 180 MHz
2. Power Consumption: 0.06 mW/MHz.
3. MIPS/MHz: 0.97
4. Architecture used: Von-Neumann. MMU
5. MPU: Not present
6. Cache Memory: Not present
7. Jazelle Instruction: Not present
8. Thumb Instruction: Yes (16 bit instruction set)
9. ARM Instruction set: Yes (32 bit)
10. ISA (Instruction Set Architecture): V4T (4 TH Version)
11. Interrupt Controller: Not Present
12. ISR entry: Non Deterministic ISR entry
13. Power Management: No in built Power Management
14. Instruction Set Performance V / 5 code size: Optimal performance code size balance requires interworking between ARM & Thumb code.
15. Ease of application porting from one device to another: Lack of standardization inhibits application porting.