Addressing modes of ARM processor are classified as follows:

Addressing modes for Data Processing Operand (i.e op1):

These are two method for addressing these operands

Unmodified value In this addressing mode, the register or a value is given unmodified i.e. without any shift or rotation e. g, (i) MOV R0, # 1234 H This instruction will move the immediate constant value 1234 into register R0.

Modified value In this addressing mode, the given value or register is shifted or rotated. These are Different shift and rotate operations possible as listed below with examples.

(1) Logical shift left This will take the value of a register and shift the value towards most Significant bits, by n bits. e.g. MOV R0, R1, LSL # 2

After the execution of this instruction R0 will become the value of R1 shifted 2 bits.

(2) Logical shift right This will take the value of a register and shift the value towards right by n bits. e.g. MOV R0, R1, LSR R2 After the execution of this instruction R0 will have the value of R1 shifted right by R2 times. R1 and R2 are not altered.

(3) Arithmetic shift right This is similar to logical shift right, except that the MSB is retained as well as shifted for arithmetic shift operation e.g. MOV R0, R1, ASR #2 After the execution of this instruction R0 will have the value of R1 Arithmetic; shifted right by 2 bits.

(4) Rotate right This will take the value of a register and rotate it right by n bits e.g. MOV R0, R1, ROR R2 After the execution of this instruction R0 will have the value of R1 rotated right for R2 times.

(5) Rotate right extended This is similar to Rotate right by one bit, with the carry flag moved into the MSB, i.e. it is similar to rotate right through carry e. g. MOV R0, R1 RRX After the execution of this instruction R0 Will have the value of register R1 rotated right through carry by 1 bit.

Addressing Modes for Memory Access Operand

As already discussed load and store instructions are used to access memory. The different memory access addressing modes are

(i) Register indirect addressing mode

(ii) Relative register indirect addressing mode

(iii) Base indexed indirect addressing mode

(iv) Base with scale register addressing mode

Each of these addressing modes have offset addressing, Pre-index addressing and post-index addressing as explained in the examples for each addressing mode

(i) Register indirect addressing mode In this addressing mode, a register is used to give the address of the memory location to be accessed. e. g. LDR R0, [R1] This instruction will load the register R0 with the 32-bit word at the memory address held in the register R1.

(ii) Relative register indirect addressing mode In this addressing mode the memory address is generated by an immediate value added to a register. Pre index and post index are supported in this addressing mode. e. g. (a) LDR R0, [R1, #4]

This instruction will load the register R0 with the word at the memory areas calculated by adding the constant address contained in the R1 register value 4 to the memory address contained in R1 register e.g. (b) LDR R0, [R1, #4]!

This is a pre-index addressing. This instruction is same \as that in e. g. (a) this instruction also places the new address in R1 i.e R1 (R1 + 4. e.g. (c)‘LDR, [R1], #4

This is post-index addressing. This instruction will load register R0 with the word at memory address given in register R1. It will then calculate the new address by adding 4 to R1 and place this new address in R1

(iii) Base indexed indirect addressing mode In this addressing mode the memory address is generated by adding the values of two registers. Pre-index and post-index are supported also in this addressing mode. e.g. (a) LDR R0, [R1, R2]

This instruction will load the register R0 with the word at memory address calculated by adding register R1 to register R2. e.g. (b) LDR R0, [R1, R2]!

This is pre-index addressing. This instruction is same as that in e.g. (a). This instruction also places the new address in R1 i. e. R1 (-R1 + R2. e.g. (c) LDR R0, [R1], R2

This is a post-index addressing. This instruction will load register R0 with the word at memory address given in register R1. It will then calculate the new address by adding the value in register R2 to register R1 and Place this new address in R1.

(iv) Base with scaled register addressing mode In this addressing mode the memory address is generated by a register value added to another register shifted left. Pre-index and post-index are supported in this addressing mode. e.g. (a) LDR R0, [R1, R2, LSL #2]

This instruction will load the register R0 with the word at the memory address calculated by adding register leith register R2 shifted left by 2 bits. e.g. (b) LDR RO,[R1, R2,_LSL #2]!

This is a pre-indexed addressing. This instruction will load the register R0 with the word at the memory address calculated by adding register R1 with register R2 shifted left by 2 bits. The new address is placed in register R1.

i.e.R1e-R1+R2 <<2.

e.g. (c) LDR R0, [R1], R2, LSL #2.

This is a post-indexed addressing. This instruction will load the register R0 with the word at memory address contained in register R1. It will then calculate the new address by adding register R1 with register R2 shifted left by two bits. The new address is placed in register.