Subject :- VLSI Design

Topic :- MOS Circuit Design Styles

Difficulty :- High

Following figure shows, the gate level representation of D-latch obtained by modifying the clocked NOR based SR latch circuit.

As shown, the circuit has single input D, which is directly connected to the S input of the latch. The input variable D is also inverted and connected to the R input of the latch.

When CLk = 1, then output Q = D &

When Clk = 0, then output will simply preserve its state.

D flip flop is used in digital circuit for temporary storage of data or as a delay element.

CMOS implementation of D-latch using $C^2$MOS

D flip flop can be implemented using Transmission gate logic.

Another method to implement D flip flop using transmission gate.