Subject :- VLSI Design

Topic :- MOS Circuit Design Styles

Difficulty :- High

1. NORA logic/ NP-Domino logic:

In domino logic, an inverter is required to connect, while NORA logic consist of alternating nMOS and pMOS stages, as shown in following figure-

As shown in figure, the precharge and evaluate timing of nMOS logic stage is accomplished by clock signal ‘Ф’ while pMOS logic stages are controlled by ϕ ̅.

Operation –

• When Ф=0, the output nodes of nMOS logic blocks are precharge to VDD through pMOS precharge transistor, whereas the output nodes of pMOS logic blocks are pre-charged to 0V through the nMOS discharge transistor, driven by Ф.
• When Ф=1, all cascaded nMOS and pMOS logic stages evaluate one after the other.

Following figure shows the scheduling of precharge/ evaluation phases.

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Advantages-

• Static CMOS inverter is not required at the output of every dynamic logic stage. Instead, a direct coupling of logic blocks is feasible by alternating nMOS and pMOS logic blocks.

• NORA logic is also compatible with domino CMOS logic.

  

2. Zipper logic

• Zipper logic is a scheme for improving charge leakage and charge sharing problems.
• Identical to NORA except the clock signals.
• It receives a slightly different clock signals for the pre-charge (discharge) transistors and for pull down (pull up) transistors.
• Clock signals which drive pMOS precharge and nMOS discharge transistors, allow the transistors to remain in weak conduction or in cutoff during evaluate phase, thus compensating for charge sharing and charge leakage problems.
• pMOS pre-charge transistors gates are held at Vdd - |Vtp|
• nMOS pre-charge transistors gates are held at Vtn above GND.