Subject :- VLSI Design

Topic :- MOS Circuit Design Styles

Difficulty :- High

The problem in clocked SR latch, in which when both inputs S and R are activated at the same time, not allowed condition comes, hence to overcome this, two feedback lines are added from the output to input as shown below, and resulting circuit is called as JK latch.

Consider any one output. From gate level diagram we can write,

For input K, assume

Therefore CMOS implementation of JK flip flop is as follows-