Subject :- VLSI Design

Topic :- MOS Circuit Design Styles

Difficulty :- High

Pseudo nMOS logic

• This technique uses single pMOS transistor with grounded gate. The logical inputs are applied to nMOS logic circuit.
• The static power dissipation is significant.
• Since the voltage swing on the output and overall functionality depends on ratio of the nMOS and pMOS transistor sizes, this circuit is called ratioed circuit.
• To get VOL as small as possible, the pMOS device should be sized much smaller than the nMOS device but it causes a negative impact on the propagation delay for changing the load since the current provided by the pMOS device is limited.
• A major disadvantage of pseudo nMOS is the static power that is dissipated when the output is low through the direct current path that exists between VDD and GND.

2 input NAND gate:

As shown in the figure below, the pMOS transistor is always ON since the gate is connected to ground.