Subject :- VLSI Design

Topic :- Semiconductor Memories

Difficulty :- High

• The row and column decoders are used to select a particular memory location in the array, based on the binary row and column addresses.
• A row decoder designed to drive a NOR ROM array must, by definition, select one of the 2N word lines by raising its voltage to VOH.

• Consider the simple row address decoder shown in Figure below which decodes a two-bit row address and selects one out of four word lines by raising its level.

  

• A most straightforward implementation of this decoder is NOR array, consisting of 4 rows (outputs) and 4 columns (two address bits and their complements). Note that this NOR-based decoder array can be built just like the NOR ROM array, using the same selective programming approach.

• The ROM array and its row decoder can be thus be fabricated as two adjacent NOR arrays, as shown. The next figure shows Row address decoder for 2 address bits and 4 word lines.

  

• The column decoder circuitry is designed to select one out of $2^M$ bit lines (columns) of the ROM array according to an M-bit column address, and to route the data content of the selected bit line to the data output.

• A nMOS pass transistor can be connected to each bit-line (column) output, and to selectively drive one out of $2^M$ pass transistors by using a NOR-based column address decoder, as shown in Figure.
• In this arrangement, only one nMOS pass transistor is turned on at a time, depending on the column address bits applied to the decoder inputs.

• The conducting pass transistor routes the selected column signal to the data output.