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Explain working of 1-T DRAM cell

Subject :- VLSI Design

Topic :- Semiconductor Memories

Difficulty :- High

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12views • Explicit Storage capacitor is manufactured per cell for data storage
• Read and Write operations are almost same.
• Write – After the word line is enabled, the data are written into the cell through M1 & stored at storage capacitor.
• The read operation is destructive. When the charge stored in the storage cell is shared with the bit line, its charge can be changed significantly (destructed).
• The capacitance of the bit line is larger than that of the storage cell by about 10 times, only a small voltage difference (based on Cs /CBL) is produced at the bit line depending on the voltage level (data) of the storage cell.
• Therefore, an amplifier to sense the signal difference (charge restoring operation) is required for the successful read operation

1. Before read operation, DL is charged to VDD/2.
2. WL is activated and thus M1 turns ON.
3. If logic 1 is stored at C1, then charge is shared with C2. Therefore there is change in voltage of DL.
4. Sense amplifier senses this change and generates valid output.
5. If voltage at DL increases, the stored bit is 1. And if voltage at DL decreases, then the stored bit is 0.
6. In DRAM cell direction of voltage change determines what is stored in cell.

WRITE operation:

1. To write 0 make DL equal to 0 or to write 1 make DL equal to 1.
2. Thus WL will be activated.
3. Based on DL the capacitor C1 is either charged or discharged.
4. If C1 is charging, logic 1 is written, and if C1 is discharging logic 0 is written.

Hold operation:

The hold time “th” is defined as the longest period of time that the cell can maintain a voltage large enough to be interpreted as logic 1; the hold time is also called the retention time.

Hold time = $t_h$ = |Δt| ≈ - $C_s$ (Δ $V_S$ /IL)

Refresh operation:

To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and then rewritten. That is perform a dummy read operation after every read or write operation. Refresh operation summary 