written 5.8 years ago by | • modified 5.5 years ago |
Subject: Basic VLSI Design
Topic: Semiconductor Memories
Difficulty: Medium
written 5.8 years ago by | • modified 5.5 years ago |
Subject: Basic VLSI Design
Topic: Semiconductor Memories
Difficulty: Medium
written 5.5 years ago by |
Consider the first 4-bit X 4bit memory array as shown in Figure below. Here, each column consists of a pseudo nMOS NOR gate driven by some of the row signals, i.e., the word line.
Only one word line is activated at a time by raising its voltage to VDD, while all other rows are held at a low voltage level.
Thus, a logic "1"-bit is stored as the absence of an active transistor, while a logic "0"-bit is stored as the presence of an active transistor at the cross point. The truth table is shown below.
Figure below shows nMOS transistors in a NOR ROM array, forming the intersection of two metal lines and two polysilicon word lines.
To store a "0"-bit at a particular address location, the drain diffusion of the corresponding transistor must be connected to the metal bit line via a metal-to-diffusion contact. Omission of this contact, on the other hand, results in stored "1"-bit.