Implement 4*4 NAND based ROM array.

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written 6.9 years ago by

hetalgosavi • 1.7k

• modified 6.7 years ago

Subject: Basic VLSI Design

Topic: Semiconductor Memories

Difficulty: Medium

vlsi design

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2.9kviews

written 6.7 years ago by

hetalgosavi • 1.7k

In this types of ROM array which is shown in Figure below each bit line consists of a depletion-load NAND gate, driven by some of the row signals, i.e. the word lines.
In normal operation, all word lines are held at the logic HIGH voltage level except for the selected …

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