written 5.8 years ago by | • modified 5.6 years ago |

**Subject:** VLSI Design

**Topic:** Data Path Design

**Difficulty:** Medium

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Explain 4 bit CLA adder implementation.

written 5.8 years ago by | • modified 5.6 years ago |

**Subject:** VLSI Design

**Topic:** Data Path Design

**Difficulty:** Medium

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written 5.6 years ago by |

Carry look-ahead (CLA) adders are designed to overcome the latency introduced by the rippling effect of the carry bits. The CLA algorithm is based on the origin of the carry-out bit in the equation.

First, if a b =1, then c = 1.

Where gi is the generate term, since the inputs are viewed as “generating” the cant-out bit. The second term represents the case where an input carry e = I may be “propagated through the full -adder. This will happen if the propagate term

is equal to 1. If P = 1 then g = 0 since the XOR operation produces a 1 the inputs are not equal. Therefore the equation becomes,

The main idea of the CLA is to first calculate the values of pi and gi for every bit, then use them to find the carry bits ci+1 once these are found, the sum bits are given by for every ‘i’.

CLA avoids the need to ripple the carry bits serially down the chain. Analyze the 4-bit CLA equations. With c0 assumed known, we have

The expressions for c2 c3 and c4 have the same form with

The first reduction is obtained by substituting C1 into the C2 equation to arrive at

Expanding,

Similarly, substituting C2 into C3 gives

Finally, the carry-out bit is

These equations show that every carry bit can be found from the generate and propagate terms. The logic diagram for the 4-bit network is as shown using the expanded expressions.

Once the carry-out bits have been calculated, the sums are found using the simple XOR operation. The complete adder circuit is shown in figure below where the CLA Network” box represents the carry bit logic in above figure.

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