Subject: VLSI Design

Topic: VLSI Clocking and System Design

Difficulty: Medium

• The CMOS chip has Electrostatic discharge protection circuit at input.
• ESD is transfer of charge between two bodies at different potentials
• ESD generates high voltage and high peak voltage and high peak current that may damage the IC. ESD occurs when two bodies at different potentials comes in direct contact or if there is high electrostatic filed between two objects that are at close proximity.

• In submicron technology, the oxide thickness is very thin, therefore the electric field is quite large

  

• As tox decreases Eox Increases also increase in VG increases Eox beyond maximum Electric field in can withstand and destroy it completely.

• There are several sources of ESD charged objects near or touching IC pins and can destroy through on-chip devices.
• Thus input protection networks are used to protect the circuit from getting destroyed due to ESD.
• As a protection, the input pads are not directly connected to the gate of MOS transistor instead and ESD protection circuit is added between the input pad and MOSFET gate.

• These networks are included as to provide an alternate change flow path to keep excessive change levels away from gate of transistor.

  

• The input protection circuits are designed to provide an alternative path for change to discharge during an ESD event.

• One of the simplest protection circuits can be realized using diodes and resistors as shown,

  

• During ESD when a highly large positive voltage is applied to input pad, D1 & D2 undergo breakdown and prevent transistor from getting damaged.

• An alternate ESD protection Circuit is shown below.

  

• The protection is achieved by clamping the excessive input voltage using diodes from input lines to voltage rail and to ground.

• During normal operation, D1 & D2 are reversed biased.
• If input voltage > rail voltage, then D1 conducts.
• If input voltage < ground voltage, then D2 conducts.