written 5.8 years ago by | • modified 5.5 years ago |
Subject: VLSI Design
Topic: VLSI Clocking and System Design
Difficulty: Medium
written 5.8 years ago by | • modified 5.5 years ago |
Subject: VLSI Design
Topic: VLSI Clocking and System Design
Difficulty: Medium
written 5.5 years ago by | • modified 5.5 years ago |
In submicron technology, the oxide thickness is very thin, therefore the electric field is quite large
As tox decreases Eox Increases also increase in VG increases Eox beyond maximum Electric field in can withstand and destroy it completely.
These networks are included as to provide an alternate change flow path to keep excessive change levels away from gate of transistor.
The input protection circuits are designed to provide an alternative path for change to discharge during an ESD event.
One of the simplest protection circuits can be realized using diodes and resistors as shown,
During ESD when a highly large positive voltage is applied to input pad, D1 & D2 undergo breakdown and prevent transistor from getting damaged.
An alternate ESD protection Circuit is shown below.
The protection is achieved by clamping the excessive input voltage using diodes from input lines to voltage rail and to ground.