Subject: Basic VLSI Design

Topic: VLSI Clocking and System Design

Difficulty: Medium

• It is always desirable to distribute clock signal over the chip area with a uniform delay.
• In order to handle high fan-out loads, the clock signals must be buffered in multiple stages.
• It is also important that every buffer stage drives the same number of fanout gate so that clock delays are always buffered.

• The figure below shows buffered clock distribution tree.

  

• Buffers amplify degraded clock signal. Due to variation of active device characteristics buffers are primary source of clock skew for a well balanced clock tree.

• Buffers provide sufficient currents to drive the network capacitance and maintain high quality clock waveforms.

Symmetric H-tree clock distribution network:

• The figure below shows general layout of H-tree clock distribution network.
• Input is applied at center of H and outputs are taken on the tips of H.

• Since the distance from center to all the branch points is same, the signal delay is same.